1. Technical Field
This invention relates generally to the field of semiconductors and, more particularly, to forming a replacement metal gate (RMG) of a semiconductor device.
2. Related Art
Metal-oxide-semiconductor (MOS) transistors using polysilicon gate electrodes are known. Polysilicon material is able to tolerate high temperature processing better than most metals, so that polysilicon can be annealed at high temperatures along with source and drain regions. In addition, polysilicon blocks ion implantation of doped atoms into a channel region, facilitating the formation of self-aligned source and drain structures after gate patterning is completed.
The high resistivities of polysilicon materials, as compared to most metal materials, result in polysilicon gate electrodes that operate at much slower speeds than gates made of metallic materials. One way of compensating for the higher resistance of polysilicon materials is to perform extensive silicide processing on the polysilicon materials so that the speed of operation of the polysilicon materials is increased to acceptable levels.
Another way of compensating for the higher resistance polysilicon materials is to replace a polysilicon gate device with a metal gate device. This replacement can be done with a replacement metal gate (RMG) process, wherein the higher temperature processing is performed while the polysilicon is present in the substrate, and, after such processing, the polysilicon is removed and replaced with metal to form the replacement metal gate. More specifically, a device with a disposable polysilicon gate is processed, and the disposable gate and dielectrics are etched away, exposing an original gate oxide. The disposable polysilicon gate is then replaced by a metal gate having lower resistivity than the polysilicon material.
RMG is desirable for achieving a device target at 20 nm and beyond. However, as gate dimensions shrink, gate resistance increases and more low-resistance metal such as tungsten (W) is needed relative to higher resistance work-function metal (WFM) such as TiN. Therefore, it is necessary for gate WFM chamfering to be performed. This is demonstrated in prior art device 100 of FIG. 1. Here, device 100 comprises a stack of layers (i.e., a substrate 102, a source/drain (S/D) layer 104 formed over the substrate, and an interlayer dielectric (IDL) layer 106 formed over the S/D layer 104), and a recess 110 formed therein. Device 100 further comprises a set of spacers 112 positioned adjacent recess 110, and a plurality of layers formed over device 100 and within recess 110, i.e., a hafnium oxide (HfO2) layer 114, a barrier layer 116 (e.g., titanium nitride (TiN)), a work-function (WF) layer 118, a capping layer 120 (e.g., TiN), and an organic dielectric layer (ODL) 122 or any other patterning mask material, which is recessed. However, tight PC dimensions make metal chamfering challenging. In this embodiment, a narrow gap (e.g., less than 2 nm) is difficult to fill in with the ODL or any other patterning mask material.
In another approach, shown in FIG. 2, a pinch-off of TiN 220 causes a seam/void 230 to form in recess 210, which results in a non-uniform or catastrophic metal recess. Therefore, this approach is also undesirable.